Sr Staff Engineer, Compiler

Japan

Engineering – Software Engineer / Full-Time / Hybrid

We're looking for an AI Compiler Engineer for a global semiconductor company delivering next-generation automotive SoC platforms with advanced AI performance for software-defined vehicles.

We're hiring an AI Compiler Engineer for their HPC team, developing compiler and code generation technologies for next-generation automotive SoCs — including advanced 3 nm silicon for software-defined vehicles — to unlock the full compute potential of Renesas hardware across multi-domain automotive applications.

About the role

In this role, you will drive compiler and code generation technologies that enable their next-generation automotive SoC platforms to deliver industry-competitive performance, efficiency, and functional safety. Your work will directly impact how AI workloads — from perception and sensor fusion to in-vehicle assistants and advanced driver assistance — are translated into highly optimized, safe, and power-efficient execution on Renesas hardware.

This position bridges software compiler development, AI model lowering and optimization, and hardware-software co-design, spanning the full path from AI workload to silicon execution. You will work across these domains to ensure Renesas SoCs meet the performance and safety requirements of multi-domain automotive applications.

We are looking for an engineer with hands-on experience in compiler development, AI model lowering, or hardware-software co-design, the ability to drive technical direction across these domains, and the foundation to deliver results on cutting-edge automotive silicon.

This role offers an opportunity for engineers who wish to work at the intersection of compilers, AI, and next-generation automotive hardware while contributing to the future of software-defined vehicles.

Responsibilities

Lead AI compiler architecture across model ingestion, graph optimization, lowering, code generation, and runtime integration
Design and implement graph‑level optimizations (operator fusion, quantization‑aware rewrites, memory‑aware scheduling, partitioning)
Drive performance optimization for target NPUs, including tiling, tensor layout, and multi‑core execution strategies
Partner with SoC and AI accelerator architects to influence hardware features through compiler insights
Own performance KPIs for real automotive AI workloads using simulators, profilers, and silicon‑correlated models
Ensure compiler outputs meet automotive requirements (real‑time behavior, determinism, quality expectations)
Mentor senior engineers and set technical direction without people‑management responsibilities

Qualifications

Required

MS/PhD (or equivalent experience) in Computer Science, EE, or related field
Deep experience building AI compilers, accelerator backends, or graph optimization frameworks
Strong expertise in graph optimization and performance optimization for NPUs or custom accelerators
Experience with MLIR, LLVM, TVM‑like systems, or proprietary compiler IRs
Excellent C/C++ and Python skills
Solid understanding of AI inference workloads (CNNs, transformers, perception or generative models)
Strong communication skills are required, e.g. agile development experience in Scrum team (Scrum Master or member)

Preferred

Experience with automotive or safety‑critical systems
Background in heterogeneous SoCs (CPU/GPU/DSP/NPU)
Performance modeling or hardware–software co‑design experience

Additional Information

Location: Kodaira, Tokyo, Japan
Work Model: Hybrid (3 days in-office, 2 days remote)
Open to relocation: This role is open to candidates located anywhere who are open to relocating to Japan

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