Senior Staff Engineer, AI Compiler

Join a global semiconductor leader building the next generation of automotive computing platforms. The company develops flagship automotive System-on-Chips (SoCs) that integrate high-performance CPUs, advanced AI accelerators, memory subsystems, high-speed connectivity, functional safety, and security technologies — enabling the future of software-defined vehicles (SDVs).

Their next-generation platforms are designed to power advanced driver assistance systems (ADAS), autonomous driving, intelligent cockpits, in-vehicle AI assistants, and connected vehicle ecosystems.

About the role

We are seeking a Senior Staff Engineer – AI Compiler to lead the development of next-generation compiler technologies that maximize the performance, efficiency, and scalability of advanced automotive AI platforms.

As a technical leader within the HPC/AI Compiler team, you will drive the architecture and implementation of compiler stacks that translate complex AI workloads into highly optimized execution pipelines across heterogeneous automotive SoCs, including advanced 3 nm silicon platforms.

Your work will directly influence how state-of-the-art AI models — including perception networks, sensor fusion pipelines, transformers, and generative AI workloads — are mapped onto custom AI accelerators and heterogeneous compute architectures.

This role sits at the intersection of:

• AI compiler architecture
• Machine learning model optimization
• Graph transformation and lowering
• Hardware-aware code generation
• Accelerator performance optimization
• Hardware/software co-design

You will define technologies that enable industry-leading performance, deterministic execution, energy efficiency, and automotive-grade reliability.

Responsibilities

• Lead the architecture and development of AI compiler technologies, including model lowering, graph optimization, code generation, and runtime integration.
• Design and implement advanced compiler optimizations for AI workloads, including operator fusion, quantization, memory optimization, scheduling, and tensor layout strategies.
• Optimize AI inference performance on heterogeneous automotive SoCs and NPUs through kernel optimization, profiling, and hardware-aware techniques.
• Own performance analysis and improvement for real-world automotive AI applications using simulators, profiling tools, and silicon feedback.
• Collaborate with SoC architects and hardware teams to drive hardware/software co-design and future accelerator innovations.
• Provide technical leadership, mentor engineers, and influence compiler architecture decisions across the organization.

Must Have

• Software Engineer with 6+ years of experience designing, developing, and maintaining scalable, high-performance applications.
• MS/PhD in Computer Science, Electrical Engineering, or a related field, or equivalent industry experience.
• Proven experience developing AI compiler stacks, accelerator compilers, graph optimization frameworks, or code generation systems.
• Strong expertise in compiler architecture, graph transformations, hardware-aware optimization, and AI inference performance tuning.
• Hands-on experience with compiler and ML frameworks such as MLIR, LLVM, TVM, XLA, or proprietary compiler infrastructures.
• Strong programming skills in C/C++ and Python.
• Deep understanding of modern AI workloads, including CNNs, transformers, computer vision, and edge AI inference.
• Excellent communication skills and experience collaborating in agile engineering environments.
• English proficiency.

Preferred Qualifications

• Experience with automotive, embedded, or safety-critical software systems.
• Knowledge of heterogeneous compute architectures (CPU/GPU/DSP/NPU) and custom AI accelerators.
• Experience with hardware/software co-design, performance modeling, compiler optimization, or silicon-level performance validation.

Additional Information

• Location: Kodaira, Tokyo, Japan
• Employment Type: Full-Time
• Work Style: On-site