Principal Engineer, RISCV Architect

Austin, TX

Engineering – Software Engineer / Full-Time / On-Site

We're hiring a Principal Engineer, RISCV Architect for a global semiconductor company developing flagship automotive SoCs — large-scale chips integrating CPU, cache, memory, high-speed interfaces, AI, video, functional safety, and security — powering the intelligence and electrification of next-generation vehicles.

About the role

We are seeking a Principal/Sr. Principal RISC-V CPU Architect with 10 to 15 years of experience to lead the architecture, development, and assessment of next-generation RISC-V processor cores. The ideal candidate will have deep expertise in high-performance CPU micro-architecture and a comprehensive understanding of the RISC-V and thorough understanding of Micro controller and micro processor architecture.

Responsibilities

Core Architecture & Specification: Define and develop detailed micro-architecture specifications for RISC-V units, including branch predictors, rename logic, instruction scheduling, and vector execution.
Design & Development: Lead the RTL development of CPU cores, ensuring alignment with power, performance, area (PPA), and timing goals.
Assessment & Benchmarking: Evaluate and benchmark various RISC-V core implementations (in-order vs. out-of-order, superscalar) against target workloads and performance models.
Virtualization & Security: Implement and optimize hardware-assisted virtualization features and architectural extensions for secure execution environments.
Infrastructure & Fabric: Architect and integrate critical infrastructure elements, including Bus fabrics (e.g., CHI, AXI), clocking, reset logic, and power management subsystems.
Full Design Flow Management: Oversee the complete design lifecycle from architectural exploration to physical design delivery, including functional and performance verification.

Qualifications

Education: Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, or a related technical field.
Experience: 10–15 years in CPU/SoC architecture and RTL design.
RISC-V Expertise: Thorough knowledge of the RISC-V ISA, including standard extensions (e.g., V-extension) and custom instruction sets.
Micro-architecture Knowledge: Deep understanding of advanced techniques such as deep pipelines, cache hierarchies, MMUs, and SIMD units. Exposure to C/SystemC based models is preferred.
Design Skills: Proficiency in Verilog/SystemVerilog and experience with simulators, waveform debuggers, and PPA optimization tools.
Systems Integration: Familiarity with modern SoC fabric protocols and the integration of infrastructure elements like PLLs and power controllers.
Mentorship: Proven ability to mentor junior architects and establish best practices across the design team.

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