Principal Engineer, Compiler

Tokyo, Japan / San Jose, California, United States / Dallas, Texas, United States

Engineering – Software Engineer / Full-Time / Hybrid

We're hiring a Principal Compiler Engineer for a global semiconductor company delivering next-generation automotive SoC platforms with advanced AI performance for software-defined vehicles.

About the role

In this role, you will lead the compiler and code generation technologies that unlock the full compute potential of Renesas' cutting-edge automotive SoCs — including advanced 3 nm silicon — directly shaping how AI workloads are translated into highly optimized, safe, and power-efficient execution on Renesas hardware.

This position centers on AI compiler architecture and hardware-software co-design — spanning model ingestion, graph optimization, lowering, and runtime integration — as well as deep performance work targeting next-generation NPUs across tiling, tensor layout, and multi-core execution. You will partner with SoC and accelerator architects to influence hardware design through compiler insights, own performance KPIs across real automotive AI workloads, and ensure outputs meet stringent automotive requirements around real-time behavior, determinism, and functional safety.

We are looking for an experienced compiler engineer with a strong background in AI compiler development, accelerator backends, or graph optimization frameworks, and deep expertise in tools such as MLIR, LLVM, or TVM-like systems, with a track record of delivering performance on NPUs or custom accelerators in demanding environments.

This role offers the chance to work at the frontier of automotive AI computing — directly enabling how perception, sensor fusion, ADAS, and in-vehicle AI workloads run on industry-leading multi-domain SoC platforms. Your work will drive competitive performance, reduce latency and energy consumption, and accelerate the adoption of AI capabilities across next-generation software-defined vehicles.

Responsibilities

Lead AI compiler architecture across model ingestion, graph optimization, lowering, code generation, and runtime integration
Design and implement graph‑level optimizations (operator fusion, quantization‑aware rewrites, memory‑aware scheduling, partitioning)
Drive performance optimization for target NPUs, including tiling, tensor layout, and multi‑core execution strategies
Partner with SoC and AI accelerator architects to influence hardware features through compiler insights
Own performance KPIs for real automotive AI workloads using simulators, profilers, and silicon‑correlated models
Ensure compiler outputs meet automotive requirements (real‑time behavior, determinism, quality expectations)
Mentor senior engineers and set technical direction without people‑management responsibilities

Qualifications

Required

MS/PhD (or equivalent experience) in Computer Science, EE, or related field
Deep experience building AI compilers, accelerator backends, or graph optimization frameworks
Strong expertise in graph optimization and performance optimization for NPUs or custom accelerators
Experience with MLIR, LLVM, TVM‑like systems, or proprietary compiler IRs
Excellent C/C++ and Python skills
Solid understanding of AI inference workloads (CNNs, transformers, perception or generative models)
Strong communication skills are required, e.g. agile development experience in Scrum team (Product Owner or Scrum Master)

Preferred

Experience with automotive or safety‑critical systems
Background in heterogeneous SoCs (CPU/GPU/DSP/NPU)
Performance modeling or hardware–software co‑design experience

Additional Information

Location: Kodaira, Tokyo, Japan
Work Model: Hybrid (3 days in-office, 2 days remote)
Open to relocation: This role is open to candidates located anywhere who are open to relocating to Japan

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