Principal AI Compiler Engineer – Automotive SoC
San Jose, CA / Dallas, TX / Tokyo
Engineering – Artificial Intelligence / Full-Time / On-Site
We’re hiring an AI Compiler Engineer for a global semiconductor company building next-generation automotive SoCs and AI acceleration platforms for software-defined vehicles. In this role, you will develop compiler and code generation technologies that translate AI workloads, such as perception, sensor fusion, in-vehicle assistants, and ADAS, into highly optimized, safe, and power-efficient execution. This position bridges software compiler development, AI model lowering and optimization, and hardware-software co-design, enabling platforms to achieve industry-leading performance, efficiency, and functional safety.
We are looking for a motivated engineer with expertise in compiler technologies, AI/ML optimization, and embedded systems who thrives at the intersection of software and hardware.
This role offers the chance to work on cutting-edge automotive AI hardware, ensuring AI models and computational kernels are efficiently mapped to silicon. Your work will directly improve performance, reduce latency and energy, and accelerate software adoption in safety-critical automotive systems.
Role Summary
As an AI Compiler Engineer on the Renesas HPC team, you will be responsible for driving compiler and code generation technologies that unlock the full compute potential of Renesas next-generation automotive System-on-Chip platforms, including advanced 3 nm silicon for software-defined vehicles (SDVs). Your work will directly impact how AI workloads — from perception and sensor fusion to in-vehicle assistants and advanced driver assistance — are translated into highly optimized, safe, and power-efficient execution on Renesas hardware. This role bridges software compiler development, AI model lowering/optimization, and hardware-software co-design, enabling Renesas SoCs to deliver industry-competitive performance, efficiency, and functional safety required by multi-domain automotive applications.
What You'll Do
Lead AI compiler architecture across model ingestion, graph optimization, lowering, code generation, and runtime integration. Design and implement graph-level optimizations (operator fusion, quantization-aware rewrites, memory-aware scheduling, partitioning). Drive performance optimization for target NPUs, including tiling, tensor layout, and multi-core execution strategies. Partner with SoC and AI accelerator architects to influence hardware features through compiler insights. Own performance KPIs for real automotive AI workloads using simulators, profilers, and silicon-correlated models. Ensure compiler outputs meet automotive requirements (real-time behavior, determinism, quality expectations). Mentor senior engineers and set technical direction without people-management responsibilities.
What We're Looking For
MS or PhD in Computer Science, EE, or related field (or equivalent experience). Deep experience building AI compilers, accelerator backends, or graph optimization frameworks.
Strong expertise in graph optimization and performance optimization for NPUs or custom accelerators. Experience with MLIR, LLVM, TVM-like systems, or proprietary compiler IRs.
Excellent C/C++ and Python skills. Solid understanding of AI inference workloads (CNNs, transformers, perception or generative models).
Strong communication skills; agile development experience in a Scrum team (Product Owner or Scrum Master role).
Strong expertise in graph optimization and performance optimization for NPUs or custom accelerators. Experience with MLIR, LLVM, TVM-like systems, or proprietary compiler IRs.
Excellent C/C++ and Python skills. Solid understanding of AI inference workloads (CNNs, transformers, perception or generative models).
Strong communication skills; agile development experience in a Scrum team (Product Owner or Scrum Master role).
Nice to Have
Experience with automotive or safety-critical systems. Background in heterogeneous SoCs (CPU/GPU/DSP/NPU).
Performance modeling or hardware-software co-design experience. LLM optimization experience (vLLM, TensorRT-LLM, ONNX Runtime). Open-source compiler or AI project contributions.
Performance modeling or hardware-software co-design experience. LLM optimization experience (vLLM, TensorRT-LLM, ONNX Runtime). Open-source compiler or AI project contributions.
Impact & Why This Role Matters
Renesas' Gen5 R-Car automotive SoC lineup, including flagship 3 nm devices like the R-Car X5H, is among the first highly integrated multi-domain automotive SoCs built on advanced 3 nm process technology, designed to run ADAS, IVI, gateway, and next-gen SDV workloads on a centralized platform. These platforms deliver high AI performance (e.g., multi-hundreds of TOPS), scalable chiplet-based acceleration, and power efficiency tailored for electrified and autonomous vehicles while meeting stringent functional safety standards. An AI Compiler Engineer enables this hardware vision by ensuring that state-of-the-art AI models and computational kernels are efficiently mapped to the silicon fabric — directly enhancing performance, reducing latency and energy, and accelerating software adoption in automotive ecosystems where compute efficiency and safety are paramount.
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