Next-gen Automotive SOC/MCU Test technology development Engineer

Japan

Engineering – Software Engineer / Full-Time / On-Site

We're hiring a Next-gen Automotive SOC/MCU Test technology development Engineer for a global semiconductor company developing flagship automotive SoCs — large-scale chips integrating CPU, cache, memory, high-speed interfaces, AI, video, functional safety, and security — powering the intelligence and electrification of next-generation vehicles.

About the role

In the increasingly competitive automotive semiconductor market, improvements in cost, quality, and time to market are crucial elements of business competitiveness. With advancements in test technology, the importance of developing common technologies that can be standardized and deployed across various products, rather than being limited to individual product-specific solutions, is growing.

This position involves working with the product development team to establish new testing technologies and deploying them as standard specifications and design assets, thereby directly contributing to the business.

They are now strengthening their engineering team to handle these challenges. This position offers a strategic role in testing new products, including 3nm generation SOCs and next-generation MCUs equipped with new non-volatile memory (such as MRAM). You will have the opportunity to contribute to the business as well as grow professionally.

They will take ownership of developing and standardizing a common test platform for next-generation automotive SoC/MCU products. This common test platform will include standardized test techniques, specifications, and reusable design assets.

Responsibilities

Responsible for planning and executing test strategies for automotive SoC/MCU products.
From conceptualizing the test mechanism to conducting actual machine evaluation and mass production application, we are able to provide consistent support.
Product application of test technologies in collaboration with product development and design teams.
Standard specifications for test techniques, design guides, reference flows, and development of reusable design assets.
As the owner of the common test infrastructure, I collaborate with design, quality, and overseas locations to promote the establishment of a standard test environment.

Qualifications

【MUST】

Practical experience (5 years or more) in semiconductor design (digital) or testing, including DFT, within the past year.
Communication skills to work collaboratively in a team
Japanese: Communication level
English: Able to understand what the other person is saying.

【WANT】

Experience in formulating test policies and creating test plans (5 years or more)
Practical experience in DFT design (SCAN, MBIST, ATPG)
Experience using HDL languages such as Verilog and VHDL.
Knowledge and interest in test methodologies and test EDA tools (Siemens, Synopsys, Cadence, etc.)

Additional Information

*Details regarding the scope of changes to the work location and the scope of duties to be performed will be provided during the selection process.

Location: Kodaira, Japan

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