DDR Interface Evaluation Leader

Japan

Engineering – Software Engineer / Full-Time / Hybrid

We're hiring a DDR Interface Evaluation Leader for a global semiconductor company developing flagship automotive SoCs — large-scale chips integrating CPU, memory, high-speed interfaces, AI, video, functional safety, and security — to support the performance and reliability of next-generation intelligent vehicles.

About the role

In this role, you will serve as a technical leader for DDR interface evaluation within a flagship automotive SoC series, driving evaluation strategy, real-hardware assessment, and signal integrity verification.

This position spans evaluation planning through hands-on execution, covering both in-house evaluation and collaboration with design teams and IP vendors. You will own the evaluation strategy from a quality assurance perspective while making technical judgments on results across performance and reliability constraints, and communicate directly with design teams and IP vendors to confirm specifications and resolve issues.

We are looking for an engineer with deep hands-on DDR interface evaluation expertise, the ability to structure technical directions and drive consensus across teams, and the communication skills to operate effectively in a collaborative development environment.

This role offers an opportunity for engineers who wish to drive SoC quality with a strong evaluation foundation while preparing to take on broader responsibilities in the future.

Responsibilities

Technically lead DDR interface (DDR IF) evaluation for automotive SoCs (R-Car series)
- Target examples: LPDDR4X/5/5X/6, DDR PHY, memory controller-related components
Drive quality and reliability assurance for DDR interfaces through real-hardware evaluation, operating margin evaluation, stress testing, and standards/guideline compliance verification
Define evaluation specifications and policies, design evaluation items and conditions, and consolidate evaluation results
Upon defect occurrence, collaborate with design teams, SoC teams, and IP vendors to lead root cause analysis and countermeasure development
Technically lead evaluation and design members in Japan, India, and Vietnam, contributing to team-wide quality improvement through clear evaluation approaches and judgment criteria

Qualifications

Required

Hands-on experience in evaluation or verification of DDR interfaces (LPDDR4/4X/5, etc.)
Experience in defect analysis, root cause identification, and countermeasure development through real-hardware evaluation, margin evaluation, and stress testing
Experience consolidating evaluation results and engaging in technical discussions and coordination with design teams and stakeholders
Knowledge and evaluation experience related to analog circuits and analog characteristics (DDR PHY, PLL, jitter, noise, SI/PI, power quality, etc.)
Ability to coordinate technically in English with design sites in India and Vietnam and with IP vendors

Preferred

Experience leading or co-leading DDR IF evaluations covering DDR PHY, memory controllers, board-level evaluation, etc
Experience measuring and analyzing DDR signals, timing, and power using oscilloscopes, logic analyzers, etc
Experience with technical inquiries, issue coordination, and evaluation result sharing with external IP vendors
Evaluation experience with automotive SoCs or products with high quality and reliability requirements
Desire to expand involvement beyond evaluation into design and broader SoC collaboration

Additional Information

Location: Kodaira, Tokyo, Japan
Work Model: Hybrid (3 days in-office, 2 days remote)
Open to relocation: This role is open to candidates located anywhere who are open to relocating to Japan

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